Codes for the transmission of data via a communications system, especially via serial busses, differ depending on the transmission medium, the bit rate and the requirement for a timing recovery and the electromagnetic compatibility (EMC) characteristic values. For instance, in order to transmit data having up to 25 megabits/s, an optical transmission was provided in the MOST system, in order to ensure the EMC. However, in this context, electrical-optical converters are very expensive, and the plastic optical fibers used make special demands on installation in the automobile body. For this purpose, the signals in the MOST bus are coded according to the Biphase Mark Code (bifrequency code). Each information bit, in this context, is represented by two code bits. If both code bits have the same value, then this value corresponds to the value of the information bit 0. A 1 is represented by different values of the code bits. In addition, after the two code bits there always takes place a change in level, independent of the information value:
code bits0010101100110101. . .info. bits01100011. . .In this context, the code has 100% redundancy compared to the message bits. However, if such a code bit sequence is transmitted via electrical lines, then, because of the frequent change of level, there takes place a large EMC emission corresponding to the bit rate (at preferably zeros) and to double the bit rate (at preferably ones). Other frequency values also come about in the frequency spectrum for the transitions between ones and zeros, without substantially attenuating the dominating two frequencies. This comes about because a level change is always called for at the bit boundaries by the coding rule. If the data are transmitted without redundancy, that is, in a binary coding having the significances 1, 2, 4, 8, etc., which may also be represented in hexadecimal coding (0×0 is equivalent to binary 0000 and 0×F is equivalent to binary 1111), this has the disadvantage that, in the first place, there does not necessarily have to be a level change (constant 0×or 0×F) or that these take place at a similar frequency as above at each bit, provided that constantly 0×5 or 0×A is transmitted. However, since there is no code redundancy in this case, but all bits are information bits, the transmission frequency may be reduced to half the value. However, in this case, this code that is used cannot have no DC component and, at the same time, does not offer the possibility of timing recovery using a PLL (phase locked loop), since there exists no specifiable maximum bit number without a level change. A phase-locked loop requires a level change for the synchronization of at least all n bits. With that, the code shows some undesired disadvantages, as was just described.
The disadvantages may be partially avoided by using a conventional block code, such as described in “A New 8B10B Block Code for High Speed Data Transmission Over Unshielded Twisted Pair Channels”, by Alistair Coles, Hewlett Packard, October 1996. In this instance the code redundancy is approximately 25%, because, instead of 8 information bits, 10 code bits are transmitted. The code has no DC component, on the average, because, as a function of the number of the transmitted ones in comparison to the zeros (running digital sum—RDS) the code word is transmitted either inverted or non-inverted. The maximum number of equal code bit values (maximum run length MRL) is 17. With that, in principle, a connection of a PLL for timing recovery would still be possible, this, however, putting high demands on the stability of the PLL, and the build-up times becoming substantially longer.
A disadvantage of the block codes is that it is not a systematic code, and consequently there is no coding rule as there is, for instance, in the case of a hexadecimal code having a significance assignment of the corresponding code bits corresponding to their position.
This has an effect especially in the implementation of an incrementer or a comparator, because first of all, especially in the case of the incrementer, the entire code word has to be received, the code value has to be ascertained by decoding using a table, and, for the code value increased by 1, the corresponding code word is generated using a table, and which then may first be emitted again, synchronized by at least one flip-flop. For the above-named block code, there comes about, through this, a delay of at least 11 clock pulses; in the case of storing the code tables in a synchronous RAM, there even comes about a delay of at least 13 clock pulses.
Thus, the conventional system does not demonstrate optimal properties in every respect.
This is true especially in regard to the properties that the code used is supposed to be with no DC component and is supposed to include frequent edges because of the required timing recovery, and is supposed to offer the possibility of serial incrementing, in order to generate the network position of a node by the simple incrementing of a special control byte and by forwarding it without great delay. In this context, it is especially desirable to find an electrical design approach which clearly has lower costs, that is, in particular, can be applied without the need of shielding within the scope of the EMC compatibility.